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introduction_to_the_xilinx_zynq_processor [2019/04/08 20:11] (current)
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 +====== Introduction to the Zynq Processor ======
  
 +
 +===== This reading assignment will acquaint you with the Xilinx Zynq processor. =====
 +
 +Answer the following questions by reading through the {{::​ds190-zynq-7000-overview.pdf|Zynq-7000 All Programmable SOC Overview}} and searching on the internet as necessary:
 +  - How many ARM cores are available?
 +  - How many DMIPS are available per core?
 +  - What is a DMIP?
 +  - How many watchdog timers are there?
 +  - What is a watchdog timer?
 +  - How many caches per core?
 +  - How many channels does the DMA controller provide?
 +  - What is a DMA controller (in general)?
 +  - How many bits in a block RAM?
 +  - What is the PL?
 +  - What is the PS?
 +  - Are the ARM cores hard or soft?
 +  - What is the NEON engine?
 +  - Do the cores provide hardware floating point support?
 +  - What is ECC and how is it implemented on Zynq?
 +  - What is AMBA and AXI (no details, just know generally what it is)?
 +  - What are the supported transfer types for DMA on Zynq?
 +  - What is the MIO?
 +  - Name to of the key features of the PL.
 +  - How big are the LUTs in the PL?
 +  - What is the FIFO controller?
 +  - What is the DSP slice?
 +  - What are the characteristics of the XADC?
introduction_to_the_xilinx_zynq_processor.txt ยท Last modified: 2019/04/08 20:11 (external edit)